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TC7126 TC7126A 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS
FEATURES
s Low Temperature Drift Internal Reference TC7126 ....................................... 80 ppm/C Typ TC7126A ..................................... 35 ppm/C Typ Guaranteed Zero Reading With Zero Input Low Noise .................................................... 15 VP-P High Resolution .............................................. 0.05% Low Input Leakage Current ...................... 1 pA Typ 10 pA Max Precision Null Detectors With True Polarity at Zero High-Impedance Differential Input Convenient 9V Battery Operation With Low Power Dissipation ........................ 500 W Typ 900 W Max
2 3 4 5 6 7
GENERAL DESCRIPTION
The TC7126A is a 3-1/2 digit CMOS analog-to-digital converter (ADC) containing all the active components necessary to construct a 0.05% resolution measurement system. Seven-segment decoders, digit and polarity drivers, voltage reference, and clock circuit are integrated on-chip. The TC7126A directly drives a liquid crystal display (LCD), and includes a backplane driver. A low-cost, high-resolution indicating meter requires only a display, four resistors, and four capacitors. The TC7126A's extremely low power drain and 9V battery operation make it ideal for portable applications. The TC7126A reduces linearity error to less than 1 count. Roll-over error (the difference in readings for equal magnitude but opposite polarity input signals) is below 1 count. High-impedance differential inputs offer 1 pA leakage current and a 1012 input impedance. The 15 VP-P noise performance guarantees a "rock solid" reading, and the auto-zero cycle guarantees a zero display reading with a 0V input. The TC7126A features a precision, low-drift internal voltage reference and is functionally identical to the TC7126. A low-drift external reference is not normally required with the TC7126A.
s s s s s s s
TYPICAL APPLICATIONS
s s s s Thermometry Bridge Readouts: Strain Gauges, Load Cells, Null Detectors Digital Meters and Panel Meters -- Voltage/Current/Ohms/Power, pH Digital Scales, Process Monitors
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION PART CODE TC7126X X XXX
A or blank*
LCD
0.1 F 34 C+ 31 33 C-
R (reversed pins) or blank (CPL pkg only) * "A" parts have an improved reference TC Package Code (see below):
1 M + ANALOG INPUT - 0.01 F
REF
REF
+ V IN
2-19 SEGMENT 22-25 DRIVE POL BP V+ 20 21 1 240 k 36 10 k + 9V
REF
- 30 V IN 32 ANALOG COMMON 28 VBUFF
MINUS SIGN BACKPLANE
Package Code
CKW CLW CPL IPL
Package
44-Pin PQFP 44-Pin PLCC 40-Pin PDIP 40-Pin PDIP (non-A only)
Temperature Range
0C to +70C 0C to +70C 0C to +70C - 25C to +85C
180 k
0.33 F 29
TC7126 TC7126A V+
0.15 F
- V REF 35 27 - 26 VINT V OSC2 OSC3 OSC1 39 38 COSC 40 ROSC 50 pF 560 k
CAZ
1 CONVERSION/SEC
AVAILABLE PACKAGES
TO ANALOG COMMON (PIN 32) NOTE: Pin numbers refer to 40-pin DIP.
40-Pin Plastic DIP
44-Pin Plastic Quad Flat 44-Pin Plastic Chip Package Formed Leads Carrier PLCC
TC7126/A-8 11/6/96
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TELCOM SEMICONDUCTOR, INC.
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3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V+ to V -)......................................... +15V Analog Input Voltage (Either Input) (Note 1) ........ V+ to V - Reference Input Voltage (Either Input) ................. V+ to V - Clock Input ...................................................... TEST to V+ Operating Temperature Range C Devices .............................................. 0C to +70C I Devices ........................................... - 25C to +85C Storage Temperature Range ................ - 65C to +150C Lead Temperature (Soldering, 10 sec) ................. +300C Power Dissipation, (TA 70C), (Note 2) 44-Pin PQFP .................................................... 1.00W 44-Pin PLCC .....................................................1.23W 40-Pin Plastic PDIP .......................................... 1.23W
*Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS: VS = +9V, fCLK = 16 kHz, and TA = +25C, unless otherwise noted.
Symbol
Input Zero Input Reading Zero Reading Drift Ratiometric Reading NL Linearity Error VIN = 0V Full Scale = 200 mV VIN = 0V, 0C TA +70C VIN = VREF, VREF = 100 mV Full Scale = 200 mV or 2V Max Deviation From Best Fit Straight Line -VIN = +VIN 200 mV VIN = 0V, Full Scale = 200 mV VIN = 0V VCM = 1V, VIN = 0V, Full Scale = 200 mV VIN = 199 mV, 0C TA +70C Ext Ref Temp Coeff = 0 ppm/C 250 k Between Common and V + 0C TA +70C ("C" Devices): TC7126 TC7126A - 25C TA +85C ("I" Device): TC7126A 250 k Between Common and V+ V + to V - = 9V V+ to V- = 9V VIN = 0V, V + to V - = 9V (Note 6) -000.0 -- 999 -1 000.0 0.2 999/1000 0.2 +000.0 1 1000 1 Digital Reading V/C Digital Reading Count
Parameter
Test Conditions
Min
Typ
Max
Unit
eN IL CMRR
Roll-Over Error Noise Input Leakage Current Common-Mode Rejection Ratio Scale Factor Temperature Coefficient
-- -- -- --
-1 15 1 50 1
0.2 -- 10 -- 5
1 Count VP-P pA V/V ppm/C
Analog Common VCTC Analog Common Temperature Coefficient
-- -- -- -- -- 2.7 4 4 --
-- -- 80 35 35 3.05 5 5 55
-- -- -- 75 100 3.35 6 6 100
-- -- ppm/C ppm/C ppm/C V VP-P VP-P A
VC LCD Drive VSD VBD
Analog Common Voltage LCD Segment Drive Voltage LCD Backplane Drive Voltage
Power Supply IS Power Supply Current
NOTES: 1. 2. 3. 4.
Input voltage may exceed supply voltages when input current is limited to 100 A. Dissipation rating assumes device is mounted with all leads soldered to PC board. Refer to "Differential Input" discussion. Backplane drive is in-phase with segment drive for "OFF" segment and 180 out-of-phase for "ON" segment. Frequency is 20 times conversion rate. Average DC component is less than 50 mV. 5. See "Typical Operating Circuit." 6. During auto-zero phase, current is 10-20 A higher. A 48 kHz oscillator increases current by 8 A (typical). Common current not included.
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3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
PIN CONFIGURATIONS
COMMON + VIN - VIN VBUFF
1
OSC 1
OSC 2
OSC 3
VREF - VREF + C REF - C REF
VREF
2
VINT
35
TEST
NC
V+
6
5
4
3
2
1
44
43
42
41
40
44 43
42
41 40 39
38
37
36
F1 7 G1 8 E1 9 D2 10
39 VREF
-
V-
34
A1
B1
C1
D1
+
+
CAZ
NC 1 NC 2 TEST 3
OSC 3 4
33 NC 32 G
+ 38 C REF - 37 C REF
36 COMMON
2
31 C 3 30 A 3 29 G 3
C2 11
+ 35 VIN
NC 5
OSC 2 6 OSC 1 7
3 4 5
NC 12 B2 13
A 2 14 F 2 15 E 2 16
TC7126CLW TC7126ACLW (PLCC)
34 NC
- 33 VIN
32 CAZ 31 VBUFF 30 VINT 29 V -
V+ 8 D1 9 C 1 10 B 1 11
12 13 14
TC7126CKW TC7126ACKW (FLAT PACKAGE)
28 BP 27 POL 26 AB 4 25 E3 24 F3 23 B3
D 3 17
18 19 20 21 22 23 24 25 26 27 28
15 16
17
18
19
20
21 22
AB4
B3
F3
E3
G3
A3
C3
POL
BP
G2
NC
D2
C2
B2
A2
A1
G1
V+ D1 C1 B1 1's A1 F1 G1 E1 D2
1 2 3 4 5 6 7 8 9
40 OSC 1 NORMAL PIN CONFIGURATION 39 OSC2 38 OSC 3 37 TEST + 36 V REF 35 V - REF + 34 CREF - 33 CREF 32 ANALOG COMMON + 31 V IN 30 V - IN 29 CAZ 28 VBUFF 27 V INT 26 V - 25 G 2 24 C 3 23 A 3 22 G 3
OSC1 OSC2 OSC 3
1 2 3
40 V + REVERSE PIN CONFIGURATION 39 D1 38 C1 37 B1 36 A1 35 F1 1's
C2 10 10's B2 11 A2 12 F2 13 E 2 14 D3 15 100's B3 16 F3 17 E 3 18 1000's AB4 19 POL 20 (MINUS SIGN)
TC7126CPL TC7126ACPL TC7126IPL TC7126AIPL
TEST 4 + V REF 5 - VREF 6 + CREF 7 - CREF 8 ANALOG 9 COMMON + V IN 10 V - 11 IN CAZ 12 VBUFF 13 V INT 14 V - 15 G 2 16
E1
34 G1 33 E 1 32 D2 TC7126RCPL TC7126ARCPL TC7126RIPL TC7126ARIPL 31 C2 30 B2 29 A2 28 F2
E2
D3
F1
F2
6
10's
27 E 2 26 D3 25 B3 24 F3 100's
7
100's
100's
C 3 17 A 3 18 G 3 19
23 E 3 22 AB4 1000's 21 POL (MINUS SIGN)
21 BP (BACKPLANE)
BP 20 (BACKPLANE)
NC = NO INTERNAL CONNECTION
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3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
PIN DESCRIPTION
40-Pin PDIP Pin Number Normal (Reverse)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (40) (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21) (20) (19) (18) (17) (16) (15) (14)
Name
V+ D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL BP G3 A3 C3 G2 V- VINT
Description
Positive supply voltage. Activates the D section of the units display. Activates the C section of the units display. Activates the B section of the units display. Activates the A section of the units display. Activates the F section of the units display. Activates the G section of the units display. Activates the E section of the units display. Activates the D section of the tens display. Activates the C section of the tens display. Activates the B section of the tens display. Activates the A section of the tens display. Activates the F section of the tens display. Activates the E section of the tens display. Activates the D section of the hundreds display. Activates the B section of the hundreds display. Activates the F section of the hundreds display. Activates the E section of the hundreds display. Activates both halves of the 1 in the thousands display. Activates the negative polarity display. Backplane drive output. Activates the G section of the hundreds display. Activates the A section of the hundreds display. Activates the C section of the hundreds display. Activates the G section of the tens display. Negative power supply voltage. The integrating capacitor should be selected to give the maximum voltage swing that ensures component tolerance build-up will not allow the integrator output to saturate. When analog common is used as a reference and the conversion rate is 3 readings per second, a 0.047 F capacitor may be used. The capacitor must have a low dielectric constant to prevent roll-over errors. See "Integrating Capacitor" section for additional details. Integration resistor connection. Use a 180 k resistor for a 200 mV full-scale range and a 1.8 M resistor for a 2V full-scale range. The size of the auto-zero capacitor influences system noise. Use a 0.33 F capacitor for 200 mV full scale, and a 0.033 F capacitor for 2V full scale. See paragraph on auto-zero capacitor for more details. The low input signal is connected to this pin. The high input signal is connected to this pin. This pin is primarily used to set the analog common-mode voltage for battery operation or in systems where the input signal is referenced to the power supply. See paragraph on analog common for more details. It also acts as a reference voltage source. See pin 34.
28 29
(13) (12)
VBUFF CAZ
30 31 32
(11) (10) (9)
VIN- VIN+ ANALOG COMMON
33
3-220
(8)
- CREF
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3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
PIN DESCRIPTION (Cont.)
40-Pin PDIP Pin Number Normal (Reverse)
34 (7)
1
2
Name
+ CREF
Description
A 0.1 F capacitor is used in most applications. If a large common-mode voltage exists (for example, the VIN- pin is not at analog common), and a 200 mV scale is used, a 1 F capacitor is recommended and will hold the roll-over error to 0.5 count. See pin 36. The analog input required to generate a full-scale output (1999 counts). Place 100 mV between pins 35 and 36 for 199.9 mV full scale. Place 1V between pins 35 and 36 for 2V full scale. See paragraph on reference voltage. Lamp test. When pulled HIGH (to V+), all segments will be turned ON and the display should read -1888. It may also be used as a negative supply for externally-generated decimal points. See paragraph under test for additional information. See pin 40. See pin 40. Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings 39per second), connect pin 40 to the junction of a 180 k resistor and a 50 pF capacitor. The 180 k resistor is tied to pin 39 and the 50 pF capacitor is tied to pin 38.
35
(6) (5)
- VREF + VREF
3 4 5
36
(4)
TEST
37 38 40
(3) (2) (1)
OSC3 OSC2 OSC1
GENERAL THEORY OF OPERATION
(All Pin Designations Refer to the 40-Pin DIP)
ANALOG INPUT SIGNAL INTEGRATOR - SWITCH DRIVER REF VOLTAGE PHASE CONTROL CONTROL LOGIC POLARITY CONTROL INTEGRATOR OUTPUT DISPLAY VIN VIN VARIABLE REFERENCE INTEGRATE TIME FIXED SIGNAL INTEGRATE TIME + COMPARATOR - VFULL SCALE 1.2 VFULL SCALE + CLOCK
Dual-Slope Conversion Principles
The TC7126A is a dual-slope, integrating analog-todigital converter. An understanding of the dual-slope conversion technique will aid in following detailed TC7126A operational theory. The conventional dual-slope converter measurement cycle has two distinct phases: (1) Input signal integration (2) Reference voltage integration (deintegration) The input signal being converted is integrated for a fixed time period (tSI), measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (tRI). In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" and "rampdown." A simple mathematical equation relates the input signal, reference voltage, and integration time: 1 RC
6 7
COUNTER
Figure 1. Basic Dual-Slope Converter
0
tSI VIN(t) dt =
VR tRI , RC
where: VR = Reference voltage tSI = Signal integration time (fixed) tRI = Reference voltage integration time (variable).
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3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
30
NORMAL MODE REJECTION (dB)
20
analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on CAZ compensates for device offset voltages. The auto-zero phase residual is typically 10 V to 15 V. The auto-zero cycle length is 1000 to 3000 clock periods.
Signal Integration Phase
10
t = MEASUREMENT PERIOD 0 0.1/t 1/t INPUT FREQUENCY 10/t
The auto-zero loop is entered and the internal differential inputs connect to VIN+ and VIN-. The differential input signal is integrated for a fixed time period. The TC7126A signal integration period is 1000 clock periods, or counts. The externally-set clock frequency is 4 before clocking the internal counters. The integration time period is: tSI = 4 fOSC 1000,
Figure 2. Normal-Mode Rejection of Dual-Slope Converter
For a constant VIN: tRI VIN = VR t . SI The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. Noise immunity is an inherent benefit. Noise spikes are integrated, or averaged, to zero during integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50 Hz/60 Hz power line period.
where fOSC = external clock frequency. The differential input voltage must be within the device common-mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, VIN- should be tied to analog common. Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than 1 LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets.
Reference Integrate Phase
The third phase is reference integrate, or deintegrate. VIN- is internally connected to analog common and VIN+ is connected across the previously-charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 internal clock periods. The digital reading displayed is: 1000 VIN VREF
ANALOG SECTION
In addition to the basic integrate and deintegrate dualslope cycles discussed above, the TC7126A design incorporates an auto-zero cycle. This cycle removes buffer amplifier, integrator, and comparator offset voltage error terms from the conversion. A true digital zero reading results without external adjusting potentiometers. A complete conversion consists of three phases: (1) Auto-zero phase (2) Signal integrate phase (3) Reference integrate phase
DIGITAL SECTION Auto-Zero Phase
During the auto-zero phase, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. Additional
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The TC7126A contains all the segment drivers necessary to directly drive a 3-1/2 digit LCD. An LCD backplane driver is included. The backplane frequency is the external clock frequency 800. For 3 conversions per second the backplane frequency is 60 Hz with a 5V nominal amplitude. TELCOM SEMICONDUCTOR, INC.
TYPICAL SEGMENT OUTPUT + V 0.5 mA SEGMENT OUTPUT LCD 2 mA
TC7126A
INTERNAL DIGITAL GROUND
BP 21 RINT - C REF V BUFF V 28 1 INTEGRATOR 7 SEGMENT DECODE - - + - ZI COMPARATOR
THOUSANDS
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS
TELCOM SEMICONDUCTOR, INC.
CAZ CINT VINT 29 27 TO DIGITAL SECTION 7 SEGMENT DECODE 7 SEGMENT DECODE 200 LCD SEGMENT DRIVERS + - VREF 35 33 ZI & AZ + AZ
HUNDREDS TENS UNITS
+ C REF
+ VREF
CREF
34
36
10 A +
ZI & AZ
DATA LATCH
+ V IN
31
INT - + V+- 2.8V CLOCK LOW TEMPCO VREF
DE (-) TO SWITCH DRIVERS FROM COMPARATOR OUTPUT fOSC
DE (+)
Figure 3. TC7126A Block Diagram
/4 26 - V 40 OSC 1 39 OSC 2 ROSC 38 OSC 3 COSC INTERNAL DIGITAL GOUND
1 6.2V CONTROL LOGIC
ANALOG COMMON
32
DE (+)
DE (-)
V
+
- V IN
AZ & DE ()
INT
TEST VTH = 1V 500 26 V-
TC7126 TC7126A
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1
7
2
6
5
4
3
8
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
When a segment driver is in-phase with the backplane signal, the segment is OFF. An out-of-phase segment drive signal causes the segment to be ON, or visible. This AC drive configuration results in negligible DC voltage across each LCD segment, ensuring long LCD life. The polarity segment driver is ON for negative analog inputs. If VIN+ and VIN- are reversed, this indicator would reverse. On the TC7126A, when the TEST pin is pulled to V+, all segments are turned ON. The display reads -1888. During this mode, LCD segments have a constant DC voltage impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE FOR MORE THAN SEVERAL MINUTES; LCDS MAY BE DESTROYED IF OPERATED WITH DC LEVELS FOR EXTENDED PERIODS. The display font and segment drive assignment are shown in Figure 4. The TC7126A is a drop-in replacement for the TC7126 and ICL7126 that offers a greatly improved internal reference temperature coefficient. No external component value changes are required to upgrade existing designs.
COMPONENT VALUE SELECTION Auto-Zero Capacitor (CAZ)
The CAZ size has some influence on system noise. A 0.33 F capacitor is recommended for 200 mV full-scale applications where 1 LSB is 100 V. A 0.033 F capacitor is adequate for 2V full-scale applications. A Mylar-type dielectric capacitor is adequate.
Reference Voltage Capacitor (CREF)
The reference voltage, used to ramp the integrator output voltage back to zero during the reference integrate phase, is stored on CREF. A 0.1 F capacitor is acceptable when VREF- is tied to analog common. If a large commonmode voltage exists (VREF- analog common) and the application requires a 200 mV full scale, increase CREF to 1 F. Roll-over error will be held to less than 0.5 count. A Mylar-type dielectric capacitor is adequate.
System Timing
The oscillator frequency is 4 prior to clocking the internal decade counters. The three-phase measurement cycle takes a total of 4000 counts (16,000 clock pulses). The 4000-count cycle is independent of input signal magnitude. Each phase of the measurement cycle has the following length: (1) Auto-zero phase: 1000 to 3000 counts (4000 to 12,000 clock pulses) For signals less than full scale, the auto-zero phase is assigned the unused reference integrate time period. (2) Signal integrate: 1000 counts (4000 clock pulses) This time period is fixed. The integration period is: tSI = 4000 1 , fOSC
Integrating Capacitor (CINT)
CINT should be selected to maximize integrator output voltage swing without causing output saturation. Due to the TC7126A's superior analog common temperature coefficient specification, analog common will normally supply the differential voltage reference. For this case, a 2V full-scale integrator output swing is satisfactory. For 3 readings per second (fOSC = 48 kHz), a 0.047 F value is suggested. For 1 reading per second, 0.15 F is recommended. If a different oscillator frequency is used, CINT must be changed in inverse proportion to maintain the nominal 2V integrator swing. An exact expression for CINT is: (4000) CINT = where: fOSC VFS RINT VINT
where fOSC is the externally-set clock frequency. (3) Reference integrate: 0 to 2000 counts (0 to 8000 clock pulses)
DISPLAY FONT
( )( )
1 fOSC VFS RINT VINT
,
1000's
100's
10's
1's
= Clock frequency at pin 38 = Full-scale input voltage = Integrating resistor = Desired full-scale integrator output swing.
Figure 4. Display Font and Segment Assignment 3-224
At 3 readings per second, a 750 resistor should be placed in series with CINT. This increases accuracy by compensating for comparator delay. CINT must have low dielectric absorption to minimize roll-over error. A polypropylene capacitor is recommended. TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
Integrating Resistor (RINT)
The input buffer amplifier and integrator are designed with Class A output stages. The output stage idling current is 6 A. The integrator and buffer can supply 1 A drive current with negligible linearity errors. RINT is chosen to remain in the output stage linear drive region, but not so large that PC board leakage currents induce errors. For a 200 mV full scale, RINT is 180 k. A 2V full scale requires 1.8 M. Component Value
CAZ RINT CINT
NOTE:
1
input voltage by two, the reference voltage should be set to 200 mV. This permits the transducer input to be used directly. The differential reference can also be used where a digital zero reading is required when VIN is not equal to zero. This is common in temperature-measuring instrumentation. A compensating offset voltage can be applied between analog common and VIN-. The transducer output is connected between VIN+ and analog common.
2 3 4 5 6 7
Nominal Full-Scale Voltage 200 mV 2V
0.33 F 180 k 0.047 F 0.033 F 1.8 M 0.047 F
DEVICE PIN FUNCTIONAL DESCRIPTION
(Pin Numbers Refer to 40-Pin DIP)
Differential Signal Inputs
VIN+ (Pin 31), VIN- (Pin 30) The TC7126A is designed with true differential inputs and accepts input signals within the input stage commonmode voltage range (VCM). Typical range is V+ -1V to V- +1V. Common-mode voltages are removed from the system when the TC7126A operates from a battery or floating power source (isolated from measured system), and VIN- is connected to analog common (VCOM). (See Figure 5.) In systems where common-mode voltages exist, the TC7126A's 86 dB common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. A worst-case condition exists if a large positive VCM exists in conjunction with a full-scale negative differential signal. The negative signal drives the integrator output positive along with VCM (see Figure 6.) For such applications, the integrator output swing can be reduced below the recommended 2V full-scale swing. The integrator output will swing within 0.3V of V+ or V- without increased linearity error.
fOSC = 48 kHz (3 readings per sec).
Oscillator Components
COSC should be 50 pF; ROSC is selected from the equation: 0.45 fOSC = RC . For a 48 kHz clock (3 conversions per second), R = 180 k. Note that fOSC is 4 to generate the TC7126A's internal clock. The backplane drive signal is derived by dividing fOSC by 800. To achieve maximum rejection of 60 Hz noise pickup, the signal integrate period should be a multiple of 60 Hz. Oscillator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz, 40 kHz, etc. should be selected. For 50 Hz rejection, oscillator frequencies of 200 kHz, 100 kHz, 66-2/3 kHz, 50 kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5 readings per second) will reject both 50 Hz and 60 Hz.
Differential Reference
VREF+ (Pin 36), VREF- (Pin 35) The reference voltage can be generated anywhere within the V+ to V- power supply range. To prevent roll-over type errors being induced by large common-mode voltages, CREF should be large compared to stray node capacitance. The TC7126A offers a significantly improved analog common temperature coefficient. This potential provides a very stable voltage, suitable for use as a voltage reference. The temperature coefficient of analog common is typically 35 ppm/C for the TC7126A and 80 ppm/C for the TC7126. ANALOG COMMON (Pin 32) The analog common pin is set at a voltage potential approximately 3V below V+. The potential is guaranteed to be between 2.7V and 3.35V below V+. Analog common is tied internally to an N-channel FET capable of sinking
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Reference Voltage Selection
A full-scale reading (2000 counts) requires the input signal be twice the reference voltage. Required Full-Scale Voltage*
200 mV 2V
*VFS = 2 VREF.
VREF
100 mV 1V
In some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, a pressure transducer output for 2000 lb/in.2 is 400 mV. Rather than dividing the TELCOM SEMICONDUCTOR, INC.
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3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
SEGMENT DRIVE LCD
MEASURED SYSTEM V+ V- V+ V -
GND
VBUFF CAZ VINT + VIN - VIN TC7126A ANALOG - + + COMMON VREF VREF V
POL BP OSC1 OSC3 OSC2 V-
GND POWER SOURCE
+ 9V
Figure 5. Common-Mode Voltage Removed in Battery Operation With VIN = Analog Common
100 A. This FET will hold the common line at 3V should an external load attempt to pull the common line toward V+. Analog common source current is limited to 1 A. Therefore, analog common is easily pulled to a more negative voltage (i.e., below V+ - 3V). - The TC7126A connects the internal V+ and VIN inIN puts to analog common during the auto-zero phase. During - the reference-integrate phase, VIN is connected to analog + common. If V IN is not externally connected to analog common, a common-mode voltage exists, but is rejected by the converter's 86 dB common-mode rejection ratio. In battery - operation, analog common and VIN are usually connected, removing common-mode voltage concerns. In systems where - VIN is connected to power supply ground or to a given - voltage, analog common should be connected to VIN. The analog common pin serves to set the analog section reference, or common point. The TC7126A is specifically designed to operate from a battery or in any measurement system where input signals are not referenced (float)
with respect to the TC7126A's power source. The analog common potential of V+ -3V gives a 7V end of battery life voltage. The common potential has a 0.001%/% voltage coefficient and a 15 output impedance. With sufficiently high total supply voltage (V+-V- >7V), analog common is a very stable potential with excellent temperature stability (typically 35 ppm/c). This potential can be used to generate the TC7126A's reference voltage. An external voltage reference will be unnecessary in most cases because of the 35 ppm/C temperature coefficient. See "TC7126A Internal Voltage Reference" discussion. TEST (Pin 37) The TEST pin potential is 5V less than V+. TEST may be used as the negative power supply connection for external CMOS logic. The TEST pin is tied to the internally-generated negative logic supply through a 500 resistor. The TEST pin load should not be more than 1 mA. See "Digital Section" for additional information on using TEST as a negative digital logic supply. If TEST is pulled HIGH (to V+), all segments plus the minus sign will be activated. DO NOT OPERATE IN THIS MODE FOR MORE THAN SEVERAL MINUTES. With TEST= V+, the LCD segments are impressed with a DC voltage which will destroy the LCD.
INPUT BUFFER + VIN - VCM + -
CI RI - + VI INTEGRATOR
TC7126A Internal Voltage Reference
The TC7126A's analog common voltage temperature stability has been significantly improved (Figure 7). The "A" version of the industry-standard TC7126 device allows users to upgrade old systems and design new systems without external voltage references. External R and C values do not need to be changed. Figure 10 shows analog common supplying the necessary voltage reference for the TC7126A. TELCOM SEMICONDUCTOR, INC.
TI VI = V CM - VIN RI CI Where: 4000 T I = Integration time = f OSC C I = Integration capacitor R I = Integration resistor
[
[
Figure 6. Common-Mode Voltage Reduces Available Integrator Swing (VCOM VIN) 3-226
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
200
ANALOG COMMON TEMPERATURE COEFFICIENT (ppm/C)
1
9V +
180 160 140 120 100 80 60 40 20 TC7126A 0
Figure 7. Analog Common Temperature Coefficient
NO MAXIMUM SPECIFIED TYPICAL
2
1 V+ 240 k 36 VREF 10 k
26 V-
NO GUARANTEED MAXIMUM SPECIFIED MAXIMUM TYPICAL
TC7126A + VREF - VREF
3 4 5 6 7
35
TYPICAL
ANALOG 32 COMMON
ICL7126 ICL7136
SET VREF = 1/2 VFULL SCALE
Figure 8. TC7126A Internal Voltage Reference Connection
APPLICATIONS INFORMATION Liquid Crystal Display Sources
Several manufacturers supply standard LCDs to interface with the TC7126A 3-1/2 digit analog-to-digital converter. Manufacturer
Crystaloid Electronics AND
Flat Package
The TC7126A is available in an epoxy 64-pin formedlead flat package. A test socket for the TC7126ACBQ device is available: Part No. IC 51-42 Manufacturer: Yamaichi Distribution: Nepenthe Distribution 2471 East Bayshore Suite 520 Palo Alto, CA 94043 (415) 856-9332
Address/Phone
5282 Hudson Dr., Hudson, OH 44236 216-655-2429 720 Palomar Avenue Sunnyvale, CA 94086 408-523-8200 1800 Vernon St., Ste. 2 Roseville, CA 95678 916-783-7878 612 E. Lake St., Lake Mills, WI 53551 414-648-2361
Representative Part Numbers*
C5335, H5535, T5135, SX440 FE 0801, FE 0203 I1048, I1126
Ratiometric Resistance Measurements
The TC7126A's true differential input and differential reference make ratiometric readings possible. In ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. No accurately-defined reference voltage is needed. The unknown resistance is put in series with a known standard and a current passed through the pair. The voltage developed across the unknown is applied to the input and the voltage across the known resistor applied to the reference input. If the unknown equals the standard, the display will read 1000. The displayed reading can be determined from the following expression: Displayed reading = RUNKNOWN RSTANDARD 1000.
VGI, Inc.
Hamlin, Inc.
3902, 3933, 3903
*NOTE:
Contact LCD manufacturer for full product listing/specifications.
Decimal Point and Annunciator Drive
The TEST pin is connected to the internally-generated digital logic supply ground through a 500 resistor. The TEST pin may be used as the negative supply for external CMOS gate segment drivers. LCD annunciators for decimal points, low battery indication, or function indication may be added without adding an additional supply. No more than 1 mA should be supplied by the TEST pin: its potential is approximately 5V below V+. TELCOM SEMICONDUCTOR, INC.
The display will overrange for RUNKNOWN 2 RSTANDARD.
3-227
8
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
Simple Inverter for Fixed Decimal Point or Display Annunciator V+ V+ 4049 TC7126A BP 21 37 GND TO BACKPLANE TO LCD DECIMAL POINT
R UNKNOWN - V IN ANALOG COMMON
Figure 10. Low Parts Count Ratiometric Resistance Measurement
R STANDARD
+ + VREF V V-
REF
+ V IN TC7126A
LCD
TEST
Multiple Decimal Point or Annunciator Driver V+ V+ BP
TC7126A
DECIMAL POINT SELECT
TO LCD DECIMAL POINTS
TEST
4030 GND
Figure 9. Decimal Point and Annunciator Drives
9V 1N4148 1 M 0.02 F 10 M 3 4 900 k C2 20V 47 k 1W 10% 6.8 F + 5 6 7 90 k 200V 20 k 10% AD636 12 11 10 9 8 2.2 F 1 M 10% 10 k + 1 F 1 2 14 13 240 k TC7126A + V REF 35 - V REF 32 ANALOG COMMON 31 + V IN 36 + V OUT V- BP
+
200 mV VIN 9 M C1 2V
26 V+ V- 27 29
1
28
40 38 39
0.01 F 30 26
10 k SEGMENT DRIVE
COM
C1 = 3 pF TO 10 pF, VARIABLE C2 = 132 pF, VARIABLE
LCD
Figure 11. 3-1/2 Digit True RMS AC DMM 3-228
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A
+ 9V 5.6 k V+ - VIN + VIN TC7126A + VREF - VREF COMMON 0.7%/C PTC R3 V- 1N4148 R1 20 k 160 k V+ - VIN + VIN R2 20 k TC7126A + VREF - VREF COMMON V- + 9V
1
160 k
300 k
300 k
2 3 4 5 6 7
1N4148 SENSOR R2 50 k
R1 50 k
Figure 12. Temperature Sensor
Figure 13. Positive Temperature Coefficient Resistor Temperature Sensor
9V
2 V+ VOUT ADJ REF02 TEMP 6 5 3
CONSTANT 5V + VREF 50 k 2- 3 TEMPERATURE DEPENDENT OUTPUT 8 1 R2 - VREF + VIN TC7126A - VIN VOUT = 1.86V @ +25C 50 k R1 COMMON V- V +
51 k R4 NC
51 k R5 1/2 LM358 + 4
GND 4
Figure 14. Integrated Circuit Temperature Sensor
8
TELCOM SEMICONDUCTOR, INC.
3-229

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